/* Copyright(c) 2006 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is iin this distribution in the
 * file called COPYING.
 *
 * Documentation: ARM DDI 0196G == PL080
 * Documentation: ARM DDI 0218E	== PL081
*
 */
        

/*
 * The AMBA DMA API is modelled on the ISA DMA API and performs
 * single asynchronous transfers between a device and memory
 * i.e. some platform fixed device address and a driver defined memory address
        

 *
 * Memory to peripheral transfer may be visualized as
 * 	Get data from memory to DMAC
 *	Until no data left
 *		On burst request from peripheral
 *			Destination burst from DMAC to peripheral
 *			Clear burst request
 *	Raise terminal count interrupt
 *
 * For peripherals with a FIFO:
 * Source      burst size == half the depth of the peripheral FIFO
 * Destination burst size == width of the peripheral FIFO
        

 *
 * (Bursts are irrelevant for mem to mem transfers - there are no burst signals)
 *
 * Details of each tranfer on a particular channel
 * are held in the DMA channel array
 * A workqueue uses those details to initiate the actual transfer
 * The DMAC interrupt clears the relevant transfer in the channel array
 *
 * ASSUMES only one DMAC device exists in the system
 * ASSUMES default (little) endianness for DMA transfers
 *
 * Only DMAC flow control is implemented
 *
 */
#include <linux/device.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/interrupt.h>

#include <linux/workqueue.h>

#include <linux/dmapool.h>
#include <asm/dma.h>
#include <asm/mach/dma.h>
#include <asm/atomic.h>
#include <asm/processor.h>
#include <linux/amba/bus.h>

#include <linux/dmaengine.h>
#include <asm/cacheflush.h>

#include <linux/amba/pl08x.h>
int ctr_chan[2];

/*
 * Predeclare the DMAENGINE API functions
 */
static int	pl08x_alloc_chan_resources(struct dma_chan *chan,
						struct dma_client *client);
static void	pl08x_free_chan_resources(struct dma_chan *chan);
static struct	dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
			struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
				size_t len, unsigned long flags);
static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
			struct dma_chan *chan, unsigned long flags);
static enum	dma_status pl08x_dma_is_complete(struct dma_chan *chan,
					dma_cookie_t cookie, dma_cookie_t *last,
						dma_cookie_t *used);
static void	pl08x_issue_pending(struct dma_chan *chan);
static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_data_direction direction,
		unsigned long flags);
static void pl08x_terminate_all(struct dma_chan *chan);

struct dma_device dmac = {
	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
	.device_free_chan_resources	= pl08x_free_chan_resources,
	.device_prep_dma_memcpy		= pl08x_prep_dma_memcpy,
	.device_prep_dma_xor		= NULL,
	.device_prep_dma_zero_sum	= NULL,
	.device_prep_dma_memset		= NULL,
	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
	.device_is_tx_complete		= pl08x_dma_is_complete,
	.device_issue_pending		= pl08x_issue_pending,
	.device_prep_slave_sg		= pl08x_prep_slave_sg,
	.device_terminate_all		= pl08x_terminate_all,
};
        

/*
 * PL08X private data structures  ==== START
 */
struct _cctl_data{
	unsigned int tsize:12;
	unsigned int sbsize:3;
	unsigned int dbsize:3;
	unsigned int swidth:3;
	unsigned int dwidth:3;
	unsigned int smaster:1;
	unsigned int dmaster:1;
	unsigned int si:1;
	unsigned int di:1;
	unsigned int prot:3;
	unsigned int intr:1;
};
union _cctl{
	struct _cctl_data bits;
	unsigned int val;
};
        

/*
 * An LLI struct - see pl08x TRM
 * Note that next uses bit[0] as a bus bit,
 * start & end do not - their bus bit info
 * is in cctl
 */
struct _lli{
	dma_addr_t src;
	dma_addr_t dst;
	dma_addr_t next;
	union _cctl cctl;
};
struct _chan_lli {
	dma_addr_t bus_list;
	void	*va_list;
};
struct pl08x_driver_data {
	void __iomem	*base;
	struct amba_device *dmac;
	struct pl08x_platform_data *pd;
	/*
	 * Single dma_pool for the LLIs
	 */
	struct dma_pool *pool;
	int pool_ctr;
	struct work_struct dwork;
	wait_queue_head_t *waitq;
	int max_num_llis;
	/*
	 * LLI details for each DMA channel
	 */
	struct _chan_lli *chanllis;
	/* Wrappers for the struct dma_chan */
	struct pl08x_dma_chan *chanwrap[MAX_DMA_CHANNELS];
	/* List of descriptors which can be freed */
	spinlock_t 		lock;
};
/*
 * PL08X private data structures  ==== END
 */
        

	这个就是DMA里面最核心的概念，LLI，Link List Item，包括了 源地址 目标地址 下一个LLI的地址 如果其为0/NULL/空，说明当前只需要传输一个信息，如果非空，传完当前的LLI，就会跳转到对应的地址，执行下一个LLI的传输 对应的控制信息cctrl - channel control 这四个值，会分别写入到对应的四个寄存器。 这样配置好了之后，再去启用DMA，DMA就会按照你的要求，把数据从源地址传送到目的地址。
	next域的值，即下一个LLI的地址，其中的bit0，是bus bit，即指示当前用哪个bus。 现将datasheet中相关解释截图如下： 图 1.1. LLI寄存器的含义 对应的bit[0],LM位，就表示了，当前使用哪个AHB master，而真正的LLI的地址，是存放在bit[2-31]
	LLI结构体，存放LLI的dma地址（供DMA控制器访问的） bus_list，和虚拟地址（普通的地址，CPU可以访问的地址），va_list
	记录对dma控制器硬件基地址ioremap之后的，驱动中可以直接访问的那个基地址 加上对应寄存器偏移量，就可以访问寄存器了
	此pl08x的DMA控制也是一个amba设备
	dma内存池，用于存放之后，每次驱动的LLI
	记录已使用内存池的数量，当达到足够大一个值的时候，做一次清理动作
	一个工作队列，后面可以看到，挂了一个函数，作用是清理释放dma pool
	将DMA 通道相关的信息，打包在这个变量里

/*
 * Power Management.
 * PM support is not complete. Turn it off.
 */
#undef CONFIG_PM

#ifdef CONFIG_PM
#else
# define pl08x_do_suspend	NULL
# define pl08x_do_resume 	NULL
# define pl08x_suspend		NULL
# define pl08x_resume		NULL
#endif

#ifdef MODULE

# error "AMBA PL08X DMA CANNOT BE COMPILED AS A LOADABLE MODULE AT PRESENT"

/*
	a) Some devices might make use of DMA during boot
	   (esp true for DMAENGINE implementation)
	b) Memory allocation will need much more attention
	   before load/unload can be supported
 */
#endif

struct pl08x_driver_data pd;

/*
 * PL08X specific defines
 */
/* Minimum period between work queue runs */
#define PL08X_WQ_PERIODMIN	20
/* Size (bytes) of each buffer allocated for one transfer */
# define PL08X_LLI_TSFR_SIZE	0x2000
/* Maximimum times we call dma_pool_alloc on this pool without freeing */
# define PL08X_MAX_ALLOCS	0x40
#define MAX_NUM_TSFR_LLIS 	(PL08X_LLI_TSFR_SIZE/sizeof(struct _lli))
#define PL08X_ALIGN		8
#define PL08X_ALLOC		0

/* Register offsets */
#define	PL08X_OS_ISR		0x00
#define	PL08X_OS_ISR_TC		0x04
#define	PL08X_OS_ICLR_TC	0x08
#define	PL08X_OS_ISR_ERR	0x0C
#define	PL08X_OS_ICLR_ERR	0x10
#define	PL08X_OS_CFG		0x30
#define	PL08X_OS_CCFG		0x10
#define	PL08X_OS_ENCHNS		0x1C
#define	PL08X_OS_CHAN		0x20
#define	PL08X_OS_CHAN_BASE	0x100

/* Channel registers */
#define	PL08X_OS_CSRC		0x00
#define	PL08X_OS_CDST		0x04
#define	PL08X_OS_CLLI		0x08
#define	PL08X_OS_CCTL		0x0C
/* register masks */
#define	PL08X_MASK_CFG		0xFFFFFFF1
#define	PL08X_MASK_EN		0x00000001
#define	PL08X_MASK_CLLI		0x00000002
#define	PL08X_MASK_TSFR_SIZE	0x00000FFF
#define	PL08X_MASK_INTTC	0x00008000
#define	PL08X_MASK_INTERR	0x00004000
#define	PL08X_MASK_CCFG		0x00000000
#define	PL08X_MASK_HALT		0x00040000
#define	PL08X_MASK_ACTIVE	0x00020000
#define	PL08X_MASK_CEN		0x00000001
#define	PL08X_MASK_ENCHNS	0x000000FF
#define PL08X_WIDTH_8BIT	0x00
#define PL08X_WIDTH_16BIT	0x01
#define PL08X_WIDTH_32BIT	0x02

/*
 * Transferring less than this number of bytes as bytes
 * is faster than calculating the required LLIs....
 * (8 is the real minimum
 * >7 bytes must have a word alignable transfer somewhere)
 */
#define PL08X_BITESIZE		0x10
/*
 * Flow control bit masks
 */
#define PL08X_FCMASK_M2M_DMA	0x00000000
#define PL08X_FCMASK_M2P_DMA	0x00000800
#define PL08X_FCMASK_P2M_DMA	0x00001000
#define PL08X_FCMASK_P2P_DMA	0x00001800
#define PL08X_FCMASK_P2P_DST	0x00002000
#define PL08X_FCMASK_M2P_PER	0x00002800
#define PL08X_FCMASK_P2P_PER	0x00003000
#define PL08X_FCMASK_P2P_SRC	0x00003800
/* Max number of transfers which can be coded in the control register */
#define PL08X_MAX_TSFRS		0xFFF

#define PL08X_CODING_ERR	0xFFFFFFFF
        

#define PL08X_CCFG_FCTL_MEM_TO_MEM		(0)
#define PL08X_CCFG_FCTL_MEM_TO_PERI		(1)
                

static unsigned int pl08x_decode_widthbits(unsigned int coded)
{
	if (coded < 3)
		return 1 << coded;

	dev_err(&pd.dmac->dev, "%s - illegal width bits 0x%08x\n", __func__,
						coded);
	return PL08X_CODING_ERR;
}
        

	根据设置的值，解码出实际位的宽度
	根据datasheet中的解释： 图 1.2. Souce Transfer Width 图 1.3. Souce or Destination Transfer Width 所以，目前只支持8.，16,32字节，位域的值分别是0，1, 2 所以此处判断小于3，才是有效的 然后1<<coded，得到的结果分别是1,2,4个字节。

static unsigned int pl08x_encode_width(unsigned int unencoded)
{
	unsigned int retval = unencoded >> 1;

	if (unencoded == (1 << retval))
		return retval;

	dev_err(&pd.dmac->dev, "%s - illegal width 0x%08x\n", __func__,
						unencoded);
	return PL08X_CODING_ERR;
}
        

/*
 * - prefers destination bus if both available
 * - if fixed address on one bus chooses other
 */
void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
	struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
	struct pl08x_bus_data **sbus, union _cctl *cctl_parm)
{
	if (!cctl_parm->bits.di) {
		*mbus = src_bus;
		*sbus = dst_bus;
	} else if (!cctl_parm->bits.si)	{
		*mbus = dst_bus;
		*sbus = src_bus;
	} else {
/* TODO: ??? */
		if (dst_bus->buswidth == 4) {
			*mbus = dst_bus;
			*sbus = src_bus;
		} else if (src_bus->buswidth == 4) {
			*mbus = src_bus;
			*sbus = dst_bus;
		} else if (dst_bus->buswidth == 2) {
			*mbus = dst_bus;
			*sbus = src_bus;
		} else if (src_bus->buswidth == 2) {
			*mbus = src_bus;
			*sbus = dst_bus;
		} else {
			/* src_bus->buswidth == 1 */
			*mbus = dst_bus;
			*sbus = src_bus;
		}
	}
}
        

int pl08x_fill_lli_for_desc(struct pl08x_txd *local_txd, int num_llis, int len,
				union _cctl *cctl, int *remainder)
{
	struct _lli *llis_va = (struct _lli *)(local_txd->llis_va);
	struct _lli *llis_bus = (struct _lli *)(local_txd->llis_bus);
	llis_va[num_llis].cctl.val	= cctl->val;
	llis_va[num_llis].src		= local_txd->srcbus.addr;
	llis_va[num_llis].dst		= local_txd->dstbus.addr;
	/*
	 * The bus bit is added to the next lli's address
	 */
	llis_va[num_llis].next =
		(dma_addr_t)((unsigned int)&(llis_bus[num_llis + 1])
					+ pd.pd->bus_bit_lli);
	if (cctl->bits.si)
		local_txd->srcbus.addr += len;
	if (cctl->bits.di)
		local_txd->dstbus.addr += len;

	*remainder -= len;

	return num_llis + 1;
}
        

	填充对应的contrl，source, destination 三个寄存器对应的值
	llis_bus[num_llis + 1]比较好理解，就是当前的LLI的next的值，应该赋值为下一个LLI 的地址
	需要特殊说明的是bus_bit_lli，此变量，意思为你当前使用DMA的哪个Master。 因为pl080内部有两个Master主控器，你在使用DMA的时候，要制定你当前是使用哪一个DMA，详情参考datasheet： 图 1.4. LLI寄存器的含义 其中32位的LLI的地址，由于是4对齐的，所以bit0和bit1肯定是0，正好利用第0位指示是master1 还是master2。 此变量不是此处pl08x DMA驱动赋值的，而是在你最开始去注册amba设备的时候赋值的。
	如果是SI，那么源地址在一次LLI的DMA传输后，源地址就应该更新，为再加上对应的每次传输的长度

/*
 * Return number of bytes to fill to boundary, or len
 */
static int pl08x_pre_boundary(int addr, int len)
{
	int boundary;

	if (len <= 0)
		dev_err(&pd.dmac->dev, "%s - zero length\n", __func__);
	boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1) << PL08X_BOUNDARY_SHIFT;

	if (boundary < addr + len)
		return boundary - addr;
	else
		return len;
}
        

#define PL08X_BOUNDARY_SHIFT	(10)	/* 1KB 0x400 */
#define PL08X_BOUNDARY_SIZE		(1 << PL08X_BOUNDARY_SHIFT)

/*
 * Note that we assume we never have to change the burst sizes
 * Return 0 for error
 */
int fill_LLIS_for_desc(struct pl08x_txd *local_txd, int pl08x_chan_num)
{
	struct pl08x_clientdev_data *client = local_txd->pcd;
	struct pl08x_bus_data *mbus, *sbus;
	int remainder;
	int num_llis = 0;
	union _cctl cctl_parm;
	int max_bytes_per_lli;
	int total_bytes = 0;
	struct _lli *llis_va;
	struct _lli *llis_bus;

	if (!local_txd) {
		dev_err(&pd.dmac->dev, "%s - no descriptor\n", __func__);
		return 0;
	}

	/*
	 * Get some LLIs
	 *  This alloc can wait if the pool is used up so we need to cleanup
	 */
	local_txd->llis_va = dma_pool_alloc(pd.pool, GFP_KERNEL,
					&local_txd->llis_bus);
	if (!local_txd->llis_va) {
		dev_err(&pd.dmac->dev, "%s - no llis\n", __func__);
		return 0;
	}

	pd.pool_ctr++;

	/*
	 * Initialize bus values for this transfer
	 * from the passed optimal values
	 */
	if (!client) {
		dev_err(&pd.dmac->dev, "%s - no client\n", __func__);
		return 0;
	}

	cctl_parm.val = client->cctl_opt;
	local_txd->srcbus.maxwidth =
		pl08x_decode_widthbits(cctl_parm.bits.swidth);

	if (local_txd->srcbus.maxwidth == PL08X_CODING_ERR) {
		dev_err(&pd.dmac->dev,
			"%s - local_txd->srcbus.maxwidth codeing error cctl_parm.bits.swidth %d\n",
				__func__, cctl_parm.bits.swidth);
		return 0;
	}

	local_txd->srcbus.buswidth = local_txd->srcbus.maxwidth;
	local_txd->dstbus.maxwidth =
		pl08x_decode_widthbits(cctl_parm.bits.dwidth);

	if (local_txd->dstbus.maxwidth == PL08X_CODING_ERR) {
		dev_err(&pd.dmac->dev,
			"%s - local_txd->dstbus.maxwidth coding error - cctl_parm.bits.dwidth %d\n",
				__func__, cctl_parm.bits.dwidth);
		return 0;
	}

	local_txd->dstbus.buswidth = local_txd->dstbus.maxwidth;

	/*
	 *  Note bytes transferred == tsize * MIN(buswidths), not max(buswidths)
	 */
	max_bytes_per_lli = min(local_txd->srcbus.maxwidth,
					local_txd->dstbus.maxwidth) *
						cctl_parm.bits.tsize;

	remainder = local_txd->len;
	/*
	 * Choose bus to align to
	 * - prefers destination bus if both available
	 * - if fixed address on one bus chooses other
	 */
	pl08x_choose_master_bus(&local_txd->srcbus,
		&local_txd->dstbus, &mbus, &sbus, &cctl_parm);

	if (local_txd->len < mbus->buswidth) {
		/*
		 * Less than a bus width available
		 * - send as single bytes
		 */
		while (remainder) {
			cctl_parm.bits.swidth = pl08x_encode_width(1);
			cctl_parm.bits.dwidth = pl08x_encode_width(1);
			cctl_parm.bits.tsize = 1;
			num_llis =
				pl08x_fill_lli_for_desc(local_txd, num_llis, 1,
					&cctl_parm, &remainder);
			total_bytes++;
		}
	} else {
		/*
		 *  Make one byte LLIs until master bus is aligned
		 *  - slave will then be aligned also
		 */
		while ((mbus->addr) % (mbus->buswidth)) {
			cctl_parm.bits.swidth = pl08x_encode_width(1);
			cctl_parm.bits.dwidth = pl08x_encode_width(1);
			cctl_parm.bits.tsize = 1;
			num_llis = pl08x_fill_lli_for_desc
				(local_txd, num_llis, 1, &cctl_parm,
					&remainder);
			total_bytes++;
		}
		/*
		 *  Master now aligned
		 * - if slave is not then we must set its width down
		 */
		if (sbus->addr % sbus->buswidth)
			sbus->buswidth = 1;

		/*
		 * Make largest possible LLIs until less than one bus width left
		 */
		while (remainder > (mbus->buswidth - 1)) {
			int lli_len, target_len;
			int tsize;
			int odd_bytes;
			/*
			 * If enough left try to send max possible,
			 * otherwise try to send the remainder
			 */
			target_len = remainder;
			if (remainder > max_bytes_per_lli)
				target_len = max_bytes_per_lli;
			/*
			 *  Set bus lengths for incrementing busses
			 *  to number of bytes which fill
			 *  to next memory boundary
			 */
			if (cctl_parm.bits.si)
				local_txd->srcbus.fill_bytes =
					pl08x_pre_boundary(
						local_txd->srcbus.addr,
						remainder);
			else
				local_txd->srcbus.fill_bytes =
					max_bytes_per_lli;
			if (cctl_parm.bits.di)
				local_txd->dstbus.fill_bytes =
					pl08x_pre_boundary(
						local_txd->dstbus.addr,
						remainder);
			else
				local_txd->dstbus.fill_bytes =
						max_bytes_per_lli;
			/*
			 *  Find the nearest
			 */
			lli_len	= min(local_txd->srcbus.fill_bytes,
						local_txd->dstbus.fill_bytes);

			if (lli_len <= 0) {
				dev_err(&pd.dmac->dev,
					"%s - lli_len is %d, <= 0\n",
						__func__, lli_len);
				return 0;
			}

			if (lli_len == target_len) {
				/*
				 * Can send what we wanted
				 */
				/*
				 *  Maintain alignment
				 */
				lli_len	= (lli_len/mbus->buswidth) *
							mbus->buswidth;
				odd_bytes = 0;
			} else {
				/*
				 * So now we know how many bytes to transfer
				 * to get to the nearest boundary
				 * The next lli will past the boundary
				 * - however we may be working to a boundary
				 *   on the slave bus
				 *   We need to ensure the master stays aligned
				 */
				odd_bytes = lli_len % mbus->buswidth;
				/*
				 * - and that we are working in multiples
				 *   of the bus widths
				 */
				lli_len -= odd_bytes;

			}
			if (lli_len) {
				/*
				 * Check against minimum bus alignment
				 */
				target_len = lli_len;
				tsize = lli_len/min(mbus->buswidth,
							sbus->buswidth);
				lli_len	= tsize * min(mbus->buswidth,
							sbus->buswidth);

				if (target_len != lli_len) {
					dev_err(&pd.dmac->dev,
					"%s - can't send what we want. Desired %d, sent %d in transfer of %d\n",
					__func__, target_len, lli_len, local_txd->len);
					return 0;
				}

				cctl_parm.bits.swidth = pl08x_encode_width
					(local_txd->srcbus.buswidth);
				cctl_parm.bits.dwidth = pl08x_encode_width
					(local_txd->dstbus.buswidth);
				if ((cctl_parm.bits.swidth == PL08X_CODING_ERR) ||
					(cctl_parm.bits.dwidth == PL08X_CODING_ERR)) {
					dev_err(&pd.dmac->dev,
					"%s - cctl_parm.bits.swidth or dwidth coding error - local_txd->dstbus.buswidth %d, local_txd->srcbus.buswidth %d\n",
					__func__,
					local_txd->dstbus.buswidth,
					local_txd->srcbus.buswidth
					);
					return 0;
				}
				cctl_parm.bits.tsize = tsize;
				num_llis = pl08x_fill_lli_for_desc(local_txd,
						num_llis, lli_len, &cctl_parm,
						&remainder);
				total_bytes += lli_len;
			}
			if (odd_bytes) {
				/*
				 * Creep past the boundary,
				 * maintaining master alignment
				 */
				int j;
				for (j = 0; (j < mbus->buswidth)
						&& (remainder); j++) {
					cctl_parm.bits.swidth =
						pl08x_encode_width(1);
					cctl_parm.bits.dwidth =
						pl08x_encode_width(1);

					cctl_parm.bits.tsize = 1;
					num_llis =
						pl08x_fill_lli_for_desc(
							local_txd, num_llis, 1,
							&cctl_parm, &remainder);
					total_bytes++;
				}
			}
		}

		/*
		 * Send any odd bytes
		 */
		if (remainder < 0) {
			dev_err(&pd.dmac->dev, "%s - -ve remainder 0x%08x\n",
					__func__, remainder);
			return 0;
		}

		while (remainder) {
			cctl_parm.bits.swidth = pl08x_encode_width(1);
			cctl_parm.bits.dwidth = pl08x_encode_width(1);
			cctl_parm.bits.tsize = 1;
			num_llis = pl08x_fill_lli_for_desc(local_txd, num_llis,
					1, &cctl_parm, &remainder);
			total_bytes++;
		}
	}
	if (total_bytes != local_txd->len) {
		dev_err(&pd.dmac->dev,
			"%s - only transferred 0x%08x from size 0x%08x\n",
				__func__, total_bytes, local_txd->len);
		return 0;
	}

	if (num_llis >= MAX_NUM_TSFR_LLIS) {
		dev_err(&pd.dmac->dev,
			"%s - need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
				__func__, MAX_NUM_TSFR_LLIS);
		return 0;
	}
	/*
	 * Decide whether this is a loop or a terminated transfer
	 */
	llis_va = ((struct _lli *)local_txd->llis_va);
	llis_bus = ((struct _lli *)local_txd->llis_bus);

	if (client->circular_buffer) {
		llis_va[num_llis - 1].next =
			(dma_addr_t)((unsigned int)&(llis_bus[0]) +
						pd.pd->bus_bit_lli);
	} else {
		/*
		 * Final LLI terminates
		 */

		llis_va[num_llis - 1].next = 0;
		/*
		 * Final LLI interrupts
		 */
		llis_va[num_llis - 1].cctl.bits.intr = PL08X_CCTL_INTR_YES;
	}

	/* Now store the channel register values */
	local_txd->csrc = llis_va[0].src;
	local_txd->cdst = llis_va[0].dst;
	if (num_llis > 1)
		local_txd->clli = llis_va[0].next;
	else
		local_txd->clli = 0;

	local_txd->cctl = llis_va[0].cctl.val;
	local_txd->ccfg = client->config_base;

	/*
	 * TODO: Change to use /proc data
	 */
	if (pd.max_num_llis < num_llis)
		pd.max_num_llis = num_llis;

	return num_llis;
}
        

/*
 * Set the initial DMA register values i.e. those for the first LLI
 * The next lli pointer and the configuration interrupt bit have
 * been set when the LLIs were constructed
 */
void pl08x_set_cregs(struct pl08x_txd *entry, int pl08x_chan_num)
{
	unsigned int reg;
	unsigned int chan_base = (unsigned int)pd.base
					+ PL08X_OS_CHAN_BASE;
	chan_base += pl08x_chan_num * PL08X_OS_CHAN;

	/* Wait for channel inactive */
	reg = readl(chan_base + PL08X_OS_CCFG);
	while (reg & PL08X_MASK_ACTIVE)
		reg = readl(chan_base + PL08X_OS_CCFG);

	writel(entry->csrc, chan_base + PL08X_OS_CSRC);
	writel(entry->cdst, chan_base + PL08X_OS_CDST);
	writel(entry->clli, chan_base + PL08X_OS_CLLI);
	writel(entry->cctl, chan_base + PL08X_OS_CCTL);
	writel(entry->ccfg, chan_base + PL08X_OS_CCFG);
	mb();
}
        

/*
 *  Might take too long to do all at once
 *  if so - free some then hand it off
 */
void pl08x_memrelease(void)
{
	struct pl08x_txd *local_txd, *next;
	unsigned long flags;
	int chan;

	for (chan = 0; chan < MAX_DMA_CHANNELS; chan++) {

		list_for_each_entry_safe(local_txd, next, &pd.chanwrap[chan]->release_list, txd_list)
		{
			spin_lock_irqsave(&pd.lock, flags);
			if (!local_txd)
				dev_err(&pd.dmac->dev,
					"%s - no descriptor\n",	__func__);

			if (local_txd->tx.callback) {
				((struct pl08x_callback_param *)
					local_txd->tx.callback_param)->act =
						PL08X_RELEASE;
				local_txd->tx.callback(
					local_txd->tx.callback_param);
			}

			list_del(&local_txd->txd_list);
			dma_pool_free(pd.pool, local_txd->llis_va,
				local_txd->llis_bus);

			/*
			 * p/m data not mapped - uses coherent or io mem
			 */
			if (!local_txd->slave) {
				dma_unmap_single(dmac.dev,
					local_txd->srcbus.addr, local_txd->len,
						local_txd->srcdir);

				dma_unmap_single(dmac.dev,
					local_txd->dstbus.addr, local_txd->len,
						local_txd->dstdir);
			}
			kfree(local_txd);
			spin_unlock_irqrestore(&pd.lock, flags);
		}
	}
	pd.pool_ctr = 0;
}
        

/*
 * Overall DMAC remains enabled always.
 *
 * Disabling individual channels could lose data.
 *
 * Disable the peripheral DMA after disabling the DMAC
 * in order to allow the DMAC FIFO to drain, and
 * hence allow the channel to show inactive
 *
 */
void pl08x_disable_dmac_chan(unsigned int ci)
{
	unsigned int reg;
	unsigned int chan_base = (unsigned int)pd.base
					+ PL08X_OS_CHAN_BASE;

	chan_base += ci * PL08X_OS_CHAN;

	/*
	 * Ignore subsequent requests
	 */
	reg = readl(chan_base + PL08X_OS_CCFG);
	reg |= PL08X_MASK_HALT;
	writel(reg, chan_base + PL08X_OS_CCFG);
    
	/* Wait for channel inactive */
	reg = readl(chan_base + PL08X_OS_CCFG);
	while (reg & PL08X_MASK_ACTIVE)
		reg = readl(chan_base + PL08X_OS_CCFG);

	reg = readl(chan_base + PL08X_OS_CCFG);
	reg &= ~PL08X_MASK_CEN;

	writel(reg, chan_base + PL08X_OS_CCFG);
	mb();

	return;
}
        

/*
 * Enable the DMA channel
 * ASSUMES All other configuration bits have been set
 *         as desired before this code is called
 */
void pl08x_enable_dmac_chan(unsigned int cnum)
{
	void __iomem *cbase = pd.base + PL08X_OS_CHAN_BASE +
					(cnum * PL08X_OS_CHAN);

	unsigned int r = 0;
	/*
	 * Do not access config register until channel shows as disabled
	 */
	while ((readl(pd.base + PL08X_OS_ENCHNS) & (1 << cnum))
			& PL08X_MASK_ENCHNS);

	/*
	 * Do not access config register until channel shows as inactive
	 */
	r = readl(cbase + PL08X_OS_CCFG);
	while ((r & PL08X_MASK_ACTIVE) || (r & PL08X_MASK_CEN))
		r = readl(cbase + PL08X_OS_CCFG);

	writel(r | PL08X_MASK_CEN, cbase + PL08X_OS_CCFG);
	mb();
}
        

static int pl08x_dma_busy(dmach_t ci)
{
	unsigned int reg;
	unsigned int chan_base = (unsigned int)pd.base
					+ PL08X_OS_CHAN_BASE;

	chan_base += ci * PL08X_OS_CHAN;

	/*
	 * Check channel is inactive
	 */
	reg = readl(chan_base + PL08X_OS_CCFG);

	return reg & PL08X_MASK_ACTIVE;
}
        

/*
 * Function for the shared work queue
 * - scheduled by the interrupt handler when sufficient
 *   list entries need releasing
 */
void pl08x_wqfunc(struct work_struct *work)
{
	if (pd.pd)
		pl08x_memrelease();
}
        

static struct amba_id pl08x_ids[] = {
	/* PL080 */
	{
		.id	= 0x00041080,
		.mask	= 0x000fffff,
	},
	/* PL081 */
	{
		.id	= 0x00041081,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

#define DRIVER_NAME	"pl08xdmac"

static int pl08x_probe(struct amba_device *amba_dev, void *id);

static struct amba_driver pl08x_amba_driver = {
	.drv.name	= "pl08xdmaapi",
	.id_table	= pl08x_ids,
	.probe		= pl08x_probe,
};
        

/*
 * This single pool easier to manage than one pool per channel
 */
int pl08x_make_LLIs(void)
{
	int ret = 0;

	/*
	 * Make a pool of LLI buffers
	 */
	pd.pool	= dma_pool_create(pl08x_amba_driver.drv.name, &pd.dmac->dev,
			PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, PL08X_ALLOC);
	if (!pd.pool) {
		ret = -ENOMEM;
		kfree(pd.chanllis);
	}
	pd.pool_ctr = 0;
	return ret;
}
        

	注意
	需要提到一点的是，如果你的驱动在初始化的时候，设置了下图： 图 2.1. 配置寄存器的含义 中的config寄存器中的ITC位，即终止计数中断，那么就会在每一个LLI传完之后就调用下面的这个pl08x_irq中断函数，如果没有设置ITC，而只是对最有一个LLI的ITC 设置了，那么就是所有的传输完成了，才会调用下面的pl08x_irq中断函数了

/*
 * issue pending() will start the next transfer
 * - it only need be loaded here
 * CAUTION the work queue function may run during the handler
 * CAUTION function callbacks may have interesting side effects
 */
static irqreturn_t pl08x_irq(int irq, void *dev)
{
	u32 mask = 0;
	u32 reg;
	unsigned long flags;
	int c;
	reg = readl(pd.base + PL08X_OS_ISR_ERR);
	mb();
	if (reg) {
		/*
		 * An error interrupt (on one or more channels)
		 */
		dev_err(&pd.dmac->dev,
			"%s - Error interrupt, register value 0x%08x\n",
				__func__, reg);
		/*
		 * Simply clear ALL PL08X error interrupts,
		 * regardless of channel and cause
		 */
		writel(0x000000FF, pd.base + PL08X_OS_ICLR_ERR);
	}
	reg = readl(pd.base + PL08X_OS_ISR);
	mb();
	for (c = 0; c < MAX_DMA_CHANNELS; c++) {
		if ((1 << c) & reg) {
			struct pl08x_txd *entry = NULL;
			struct pl08x_txd *next;

			spin_lock_irqsave(&pd.chanwrap[c]->lock, flags);

			if (pd.chanwrap[c]->at) {
				/*
				 * Update last completed
				 */
				pd.chanwrap[c]->lc =
					(pd.chanwrap[c]->at->tx.cookie);
				/*
				 * Callback peripheral driver for p/m
				 * to signal completion
				 */
				if (pd.chanwrap[c]->at->tx.callback) {
					/*
					 * Pass channel number
					 */
					((struct pl08x_callback_param *)
						pd.chanwrap[c]->at->tx.callback_param)->act = c;
					pd.chanwrap[c]->at->tx.callback(
						pd.chanwrap[c]->at->tx.callback_param);
				}
				/*
				 * Device callbacks should NOT clear
				 * the current transaction on the channel
				 */
				if (!pd.chanwrap[c]->at)
					BUG();

				/*
				 * Free the descriptor if it's not for a device
				 * using a circular buffer
				 */
				if (!(pd.chanwrap[c]->at->pcd->circular_buffer)) {
					list_add_tail(&pd.chanwrap[c]->at->txd_list,
						&pd.chanwrap[c]->release_list);
					pd.chanwrap[c]->at = NULL;
					if (pd.pool_ctr > PL08X_MAX_ALLOCS) {
						schedule_work(&pd.dwork);
					}
				}
				/*
				 * else descriptor for circular
				 * buffers only freed when
				 * client has disabled dma
				 */
			}
			/*
			 * If descriptor queued, set it up
			 */
			if (!list_empty(&pd.chanwrap[c]->desc_list)) {
				list_for_each_entry_safe(entry,
				next, &pd.chanwrap[c]->desc_list, txd_list) {
					list_del_init(&entry->txd_list);
					pd.chanwrap[c]->at = entry;
					break;
				}
			}

			spin_unlock_irqrestore(&pd.chanwrap[c]->lock, flags);

			mask |= (1 << c);
		}
	}
	/*
	 * Clear only the terminal interrupts on channels we processed
	 */
	writel(mask, pd.base + PL08X_OS_ICLR_TC);
	mb();

	return mask ? IRQ_HANDLED : IRQ_NONE;
}
        

static void pl08x_ensure_on(void){
	unsigned int reg;

	reg = readl(pd.base + PL08X_OS_CFG);
	reg &= PL08X_MASK_CFG;
	reg |= PL08X_MASK_EN;
	mb();
	writel(reg, pd.base + PL08X_OS_CFG);
	mb();
}
        

/*
 * Initialise the DMAC channels.
 * Make a local wrapper to hold required data
 */
static int pl08x_dma_enumerate_channels(void)
{
	int dma_chan;
	struct pl08x_dma_chan *local_chan;

	dma_cap_set(DMA_MEMCPY, dmac.cap_mask);
	dma_cap_set(DMA_SLAVE, dmac.cap_mask);
	if (dmac.chancnt)
		dev_err(&pd.dmac->dev, "%s - chancnt already set\n", __func__);
	INIT_LIST_HEAD(&dmac.channels);

	for (dma_chan = 0; dma_chan < MAX_DMA_CHANNELS; dma_chan++) {

		local_chan = kzalloc(sizeof(struct pl08x_dma_chan),
					GFP_KERNEL);
		if (!local_chan) {
			dev_err(&pd.dmac->dev,
				"%s - no memory for channel\n", __func__);
			return dmac.chancnt;
		}

		/*
		 * Save the DMAC channel number
		 * to indicate which registers to access
		 */
		local_chan->chan_id = dma_chan;
		local_chan->chan.device = &dmac;
		atomic_set(&local_chan->last_issued, 0);
		local_chan->lc = atomic_read(&local_chan->last_issued);
		if (pd.pd->reserved_for_slave)
			local_chan->slave_only = pd.pd->reserved_for_slave(dma_chan);
		else
			dev_err(&pd.dmac->dev,
				"%s - can't establish channels reserved for slaves\n",
					__func__);

		spin_lock_init(&local_chan->lock);
		INIT_LIST_HEAD(&local_chan->desc_list);
		INIT_LIST_HEAD(&local_chan->release_list);

		list_add_tail(&local_chan->chan.device_node, &dmac.channels);

		pd.chanwrap[dmac.chancnt++] = local_chan;
	}

	return dmac.chancnt;
}
        

static int pl08x_probe(struct amba_device *amba_dev, void *id)
{
	int ret = 0;

	ret = pl08x_make_LLIs();
	if (ret)
		return -ENOMEM;

	ret = amba_request_regions(amba_dev, NULL);
	if (ret)
		return ret;

	pd.max_num_llis = 0;

	/*
	 * We have our own work queue for cleaning memory
	 */
	INIT_WORK(&pd.dwork, pl08x_wqfunc);
	pd.waitq = kmalloc(sizeof(wait_queue_head_t), GFP_KERNEL);
	init_waitqueue_head(pd.waitq);

	spin_lock_init(&pd.lock);

	pd.base = ioremap(amba_dev->res.start, SZ_4K);
	if (!pd.base) {
		ret = -ENOMEM;
		goto out1;
	}
	/*
	 * Attach the interrupt handler
	 */
	writel(0x000000FF, pd.base + PL08X_OS_ICLR_ERR);
	writel(0x000000FF, pd.base + PL08X_OS_ICLR_TC);
	mb();

	ret = request_irq(amba_dev->irq[0], pl08x_irq, IRQF_DISABLED,
			DRIVER_NAME, &amba_dev->dev);
	if (ret) {
		dev_err(&pd.dmac->dev, "%s - Failed to attach interrupt %d\n",
				__func__, amba_dev->irq[0]);
		goto out2;
	}
	/*
	 * Data exchange
	 */
	pd.dmac = amba_dev;
	amba_set_drvdata(amba_dev, &pd);
	pd.pd = (struct pl08x_platform_data *)(amba_dev->dev.platform_data);
	/*
	 * Negotiate for channels with the platform
	 * and its DMA requirements
	 */
	dmac.dev = &amba_dev->dev;

	ret = pl08x_dma_enumerate_channels();

	if (!ret) {
		dev_warn(&pd.dmac->dev,
			"%s - failed to enumerate channels - %d\n",
				__func__, ret);
		goto out2;
	} else {
		ret = dma_async_device_register(&dmac);
		if (ret) {
			dev_warn(&pd.dmac->dev,
				"%s - failed to register as an async device - %d\n",
					__func__, ret);
			goto out2;
		}
	}
	pl08x_ensure_on();
	dev_info(&pd.dmac->dev,
		"%s - ARM(R) PL08X DMA driver found\n",
			__func__);

	goto out;
out2:
	iounmap(pd.base);
out1:
	amba_release_regions(amba_dev);
out:
	return ret;
}
        

static int __init pl08x_init(void)
{
	int retval;
	retval = amba_driver_register(&pl08x_amba_driver);
	if (retval)
		printk(KERN_WARNING
			"PL08X::pl08x_init() - failed to register as an amba device - %d\n",
				retval);
	return retval;
}
device_initcall(pl08x_init);
        

/* ===============================================================
 * The DMA ENGINE API
 * ===============================================================
 */
static int pl08x_alloc_chan_resources(struct dma_chan *chan,
					struct dma_client *client)
{
	struct pl08x_dma_chan *local_chan = container_of
				(chan, struct pl08x_dma_chan, chan);

	int assigned = 0;
	/*
	 * Channels may be reserved for slaves
	 * Channels doing slave DMA can only handle one client
	 */
	if (local_chan-<slave_only) {
		if (!client-<slave)
			return -EBUSY;
	} else	if (client-<slave)
		return -EBUSY;


	/* Slave DMA clients can only use one channel each */
	if ((client-<slave) && (chan-<client_count))
		return -EBUSY;
	else {
		/* Channels doing slave DMA can only handle one client. */
		if ((local_chan-<slave) && (chan-<client_count)) {
			dev_err(&pd.dmac-<dev,
				"%s - channel %d already has a slave - local_chan-<slave %p\n",
					__func__,
					local_chan-<chan_id,
					local_chan-<slave);
			return -EBUSY;
		}

		/* Check channel is idle */
		if (pl08x_dma_busy(local_chan-<chan_id)) {
			dev_err(&pd.dmac-<dev,
				"%s - channel %d not idle\n",
					__func__, local_chan-<chan_id);
			return -EIO;
		}
		local_chan-<slave = client-<slave;
	}

	return assigned;
}
        

static void pl08x_free_chan_resources(struct dma_chan *chan)
{
	dev_warn(&pd.dmac->dev, "%s - UNIMPLEMENTED\n", __func__);
}
        

/*
 * First make the LLIs (could/should we do this earlier??)
 * slave (m/p) - no queued transactions allowed at present
 *	TODO allow queued transactions for non circular buffers
 * Set up the channel active txd as inactive
 * m2m	- transactions may be queued
 * If no active txd on channel
 *	set it up as inactive
 *	- issue_pending() will set active & start
 * else
 *	queue it
 * Lock channel since there may be (at least for m2m) multiple calls
 *
 * Return < 0 for error
 */
static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
{
	int num_llis;
	unsigned long flags;
	struct pl08x_txd *local_txd = container_of(tx, struct pl08x_txd, tx);
	struct pl08x_dma_chan *local_chan =
			container_of(tx->chan, struct pl08x_dma_chan, chan);
	int pl08x_chan_num = local_chan->chan_id;
	num_llis = fill_LLIS_for_desc(local_txd, pl08x_chan_num);

	if (num_llis) {
		spin_lock_irqsave(&local_chan->lock, flags);
		atomic_inc(&local_chan->last_issued);
		tx->cookie = atomic_read(&local_chan->last_issued);

		if (local_chan->at) {

			/*
			 * If this device not using a circular buffer then
			 * queue this new descriptor.
			 * The descriptor for a circular buffer continues
			 * to be used until the channel is freed
			 */
			if (local_txd->pcd->circular_buffer)
				dev_err(&pd.dmac->dev,
					"%s - attempting to queue a circular buffer\n",
						__func__);
			else
				list_add_tail(&local_txd->txd_list,
					&local_chan->desc_list);

		} else {
			local_txd->slave = local_chan->slave;
			local_chan->at = local_txd;
			local_txd->active = 0;
		}

		spin_unlock_irqrestore(&local_chan->lock, flags);

		return tx->cookie;
	} else
		return -EINVAL;
}
        

/*
 * Initialize a descriptor to be used by submit
 */
static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
		size_t len, unsigned long flags)
{
	struct pl08x_txd *local_txd;
	local_txd = kzalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
	if (!local_txd) {
		dev_err(&pd.dmac->dev,
			"%s - no memory for descriptor\n", __func__);
		return NULL;
	} else {
		dma_async_tx_descriptor_init(&local_txd->tx, chan);
		local_txd->srcbus.addr	= src;
		local_txd->dstbus.addr	= dest;
		local_txd->tx.tx_submit	= pl08x_tx_submit;
		local_txd->len = len;
		/*
		 *  dmaengine.c has these directions hard coded,
		 *  but not acessible
		 */
		local_txd->dstdir = DMA_FROM_DEVICE;
		local_txd->srcdir = DMA_TO_DEVICE;
		INIT_LIST_HEAD(&local_txd->txd_list);
		/*
		 * Ensure the platform data for m2m is set on the channel
		 */
		local_txd->pcd = &pd.pd->sd[PL08X_DMA_SIGNALS];
	}
	return &local_txd->tx;
}
        

static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
		struct dma_chan *chan, unsigned long flags)
{
	struct dma_async_tx_descriptor *retval = NULL;
	return retval;
}
        

/*
 * Code accessing dma_async_is_complete() in a tight loop
 * may give problems - could schedule where indicated.
 * If slaves are relying on interrupts to signal completion this
 * function must not be called with interrupts disabled
 */
static enum dma_status pl08x_dma_is_complete(struct dma_chan *chan,
						dma_cookie_t cookie,
						dma_cookie_t *done,
						dma_cookie_t *used)
{
	struct pl08x_dma_chan *local_chan = container_of(chan,
				struct pl08x_dma_chan, chan);
	dma_cookie_t last_used;
	dma_cookie_t last_complete;
	enum dma_status ret;

	last_used = atomic_read(&local_chan->last_issued);
	last_complete = local_chan->lc;

	if (done)
		*done = last_complete;
	if (used)
		*used = last_used;

	ret = dma_async_is_complete(cookie, last_complete, last_used);
	if (ret == DMA_SUCCESS)
		return ret;

	/*
	 * schedule(); could be inserted here
	 */

	/*
	 * This cookie not complete yet
	 */
	last_used = atomic_read(&local_chan->last_issued);
	last_complete = local_chan->lc;

	if (done)
		*done = last_complete;
	if (used)
		*used = last_used;

	return dma_async_is_complete(cookie, last_complete, last_used);
}
        

/*
 * Slave transactions callback to the slave device to allow
 * synchronization of slave DMA signals with the DMAC enable
 */
static void pl08x_issue_pending(struct dma_chan *chan)
{
	struct pl08x_dma_chan *local_chan
		= container_of(chan, struct pl08x_dma_chan, chan);
	int pl08x_chan_num = local_chan->chan_id;

	if (local_chan->at) {
		if (!local_chan->at->active) {
			pl08x_set_cregs(local_chan->at, local_chan->chan_id);
			if (local_chan->slave) {
				/*
				 * Allow slaves to activate signals
				 * concurrent to the DMAC enable
				 */
				if (local_chan->at->tx.callback) {
					((struct pl08x_callback_param *)
						local_chan->at->tx.callback_param)->act =
								PL08X_SIGNAL_START;
					local_chan->at->tx.callback(
						local_chan->at->tx.callback_param);
				}
			}
			pl08x_enable_dmac_chan(local_chan->chan_id);
			local_chan->at->active = 1;
		}
		/*
		 * else skip active transfer
		 * Calls with active txd occur for NET_DMA
		 * - there can be queued descriptors
		 */
	}
	/*
	 * else - calls with no active descriptor occur for NET_DMA
	 */
}
        

struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_data_direction direction,
		unsigned long flags)
{
	struct pl08x_txd *local_txd;
	unsigned int reg = 0;
	int i;

	/*
	 * Current implementation ASSUMES only one sg
	 */
	if (sg_len != 1)
		BUG();

	local_txd = kmalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
	if (!local_txd)	{
		dev_err(&pd.dmac->dev, "%s - no local_txd\n", __func__);
		return NULL;
	} else {
		struct pl08x_dma_chan *local_chan =
			container_of(chan, struct pl08x_dma_chan, chan);

		dma_async_tx_descriptor_init(&local_txd->tx, chan);

		if (direction == DMA_TO_DEVICE) {

			local_txd->srcbus.addr	= sgl->dma_address;
			local_txd->dstbus.addr	=
				reg = local_chan->slave->tx_reg;

		} else if (direction == DMA_FROM_DEVICE) {
			local_txd->srcbus.addr	=
				reg = local_chan->slave->rx_reg;
			local_txd->dstbus.addr	= sgl->dma_address;
		} else {
			dev_err(&pd.dmac->dev,
				"%s - direction unsupported\n", __func__);
			return NULL;
		}
		/*
		 * Find the device array entry for this txd
		 * so that the txd has access to the peripheral data
		 */
		for (i = 0; i < PL08X_DMA_SIGNALS; i++) {
			if (reg == (((unsigned int)(pd.pd->sd[i].io_addr))))
				break;
		}
		local_txd->pcd = &pd.pd->sd[i];
		local_txd->tx.tx_submit	= pl08x_tx_submit;
		local_txd->len = sgl->length;
		INIT_LIST_HEAD(&local_txd->txd_list);
	}

	return &local_txd->tx;
}
        

/*
 * CAUTION: Called by ALSA interrupt handler
 */
void pl08x_terminate_all(struct dma_chan *chan)
{
	struct pl08x_dma_chan *local_chan =
		container_of(chan, struct pl08x_dma_chan, chan);
	int pl08x_chan_num = local_chan->chan_id;

	if (local_chan->slave->dev) {
		pl08x_disable_dmac_chan(pl08x_chan_num);
		/*
		 * Allow slaves to activate signals
		 * concurrent to the DMAC enable
		 */
		if (local_chan->at) {
			if (local_chan->at->tx.callback) {
				((struct pl08x_callback_param *)
					local_chan->at->tx.callback_param)
						->act = PL08X_SIGNAL_STOP;

				local_chan->at->tx.callback(
					local_chan->at->tx.callback_param);
			}
		}
	}
}