….
[20090916]
1.write the uImage into VFP.
2.move the LBA driver into as3527, only add basic code…
[20090911]
1.try write without ecc, result is OK, no error.
try read, but failed, later find that can not read status and return to read mode, so failed.
remove read status, then read data is OK.
found the ecc from LBA is not the same with the ecc from NAND controller,
later find that our previous code to read ECC from nand controller, not make sure the mode is compatile with discription in datasheet, which need the mode is ECC stop, not ecc disable.
so set ecc stop before read ecc, and if not set ECC disable after read ecc,then follow read status will failed.then ecc is OK.
So, finnally make the LBA MDP mode read and write both OK.
[20090910]
1.continue to debug the LBA write for MDP mode. found the write error after write, while if disable ECC correct , then write is OK.
[20090909]
1.find VBR patch for mplayer 1.0 rc1 and rc2 both not work well now …. so to be checked later …
find set :
–enable-largefiles enable support for files > 2GB [disable]
can enable the off_t to long long while use –disable-mpdvdkit, but still not work well. So more debug need…
[20090908]
1.basicly generate the VBR patch for Mplayer 1.0 rc1 and rc2, but rc1 has some problem with lib mad display the total play time of VBR mp3. need to be fixed.
[20090907]
1.in the end, no solution for boot from LBA nand, the most successfully situation is, for 2048 data, the read out data is 512 data then 16 oob, then following 512+16+512+16, so the last is only 512-48 valid data..
2. so not continue to do this, directly go to realisze the LBA MDP mode read and write.
till now, the write func not work well… to be fixed later..
[20090904]
1.realize the LBA PNP partial page read&write for Boot Mode 1/2/3 and normal data layout mode.
but in the end, the test result is only the Mode 3 and write to second block address 0x20000, the bootcode in ROM can readout the fisrt 512 bytes of 2048 one page.other mode can not read out useful data but 0xFF. more concern should to be consider to test whether can boot from LBA nand later…
[20090903]
1.make the PNP page read and write work. but want to makesure can boot from LBA nand need write data according to the 3 boot mode and check which can boot .
[20090902]
1.basicly write done the PNP read/write and LBA read/write, but not run to test now.
[20090901]
1.continue to write LBA PNP write function.
2.make mplayer display the play time of VBR MP3 normally, by use MP3 VBR patch and edit a file in mad lib.
[20090831]
1.make LBA nand read ID1 and ID2, and issue common command, such as ：
In BCM mode :get/Set boot Mode, get/set reboot command, get Device attribute data
In MDP mode : get MDP and VFP size.
2.use cracked Jlink to Burn external Nor Flash on AS3527.
【20090829-20090830】
1.see LBA nand flash datasheet.
[20090828]
1.done use the UID as MAC address both in Uboot and kernel.
2.begin do the LBA nand flash driver in uboot.
[20090827]
1.burn uImage into Nor Flash, then when uboot read uImage from Nor into SDRAM, then do bootm.
when boot kernel not from NFS, so not need init ENC Ethernet, so not need read MAC before jump to Linux from uboot.
2.use the chip UID to be MAC address for uboot and kernel.
in uboot is simple,just add code to read UID and subtitute the macro defined MAC address when init gd->bd->bi_enetaddr.But for kernel, for the read UID function is after the AFE init, so we need to move the afre init code before SSP init, in which ENC initalize.
Unfotunately, when move the afe related init code into level 5, before all the modules init, the read UID is OK when init enc driver, but later net not work well.
so we only can do is move afe init code into proper position. Just before ENC init and after needed init for AFE.
[20090826]
1.during debug, find the RVDS debug tools memory tools show the Nor flash (0x10000000) content is normal just after open debug tools, but will change when load the sysbols and uboot binary file, finnally find when update the nor flash content,(try to write/read into any address of nor) some content will change.in the end found the voltage of VDD_PERI(Nor’s vdd) is only 1.8V, not 3.3V, so work not normally. after do hardware change for as3527 board, let it Open mode, then after power-of-reset, the vdd is OK, and add a jumper, connect the VDD_PERI pin with VDD_MEM ,so let Nor flash work well.
2.then compile a new uboot.bin with code copy, then write the uboot.bin into Nor by RVDS debug throught cp.b command in uboot. set board boot from external Nor Flash/Static Memory
then add code in start.S, to copy the code from Nor Flash, after code copy, set CCU_MEMMAP to remap the SRAM into 0x0 address, while current 0x0 is Nor flash, then can continue to run code in SRAM. can normally boot the uboot now !!!
[20090825]
1.after realize the write command for nor flash,
found the uboot has support this by :
cp mem-addr flash-addr len
so not use the command I have realize anymore.
use cp.b 0x31000000 0x10000000 0x25a74
to burn the uboot which I load into 0x31000000
into flash which base address is 0x10000000
but by debug find the write function of nor flash is big endian,
so change the half-word data into little endian before real write operation.
after correct burn uboot into nor,
then want to boot uboot from nor.
so goto change lds file, want to change the data, bss … segment into embedded 320KB 1T-RAM.
but failed for data segment, but OK for bss segment.
after find it is difficult to realize boot uboot from nor,
then try to use another method: port our SDK12 LBA nand flash driver into current SDK7 for as3527,
but found is so complicated, not easy to port, so give off this method.
next step is continue to research how to copy uboot code from nor into SRAM, then remap 0x0 to SRAM
then jump into 0x0 to run uboot in SRAM.
[20090824]
1.thought can simply realize the erase and write function for Nor flash after the successful of read Manufacture ID and decvice ID,
but finnaly find it is far more to do,
and chech out that if I debug to run code, then the code work well,
but if I let it run normally, it failed to erase and timeout.
I thought it’s the time between two sending command to erase, so add udelay, but no effect.
and enlarge the wait time between write operation, also no use.
At the end, my leader solve this problem by make the time out time larger, which previously is
defined to 200*1000 ms, but actually is far less than that.
the detailed reason to be find later if has enough time.
before get off work, got the uboot burn into Nor but seems not fully correct.
Next to be done now is get the uboot burn into Nor flash correctly, and boot successfully from Nor.
[20090821]
1.try to burn uboot into nor flash. after many time debug,
to verify the clock of Nor Flash/Static Memory, verify the nor flash’s voltage:vdd_peri, verify the sram configure in uboot, and finnaly configure to X16 device and refer other architechture’s code for X16, then can read out the Manufacture ID and device ID.
[20090820]
1.verify the as3527 board RTC work OK, which verify that:
rtc driver has to find out the hardware is 25/27, and the hwclock seems can work but the rtc time is not change.so to verify the rtc’s crystal oscillator is installed on board, and verify the RTC voltage is OK, then in then end found out the jumper wire is not available, so not enable the rtc, after got a jumper wire and install it the rtc work OK.
2.change the keyboard driver , to make keyboard work well for 4X4 keys.
[20090819]
1.retain the icache to keep cpu read speed, and to solve the net not work in kernel.
in the end, we find out that if we read once MAC address before jump to kernel from uboot, then the net work well in kernel. details refer article in my blog.
[20090818]
1.finnaly find out that the ethernet is not work due to the open of ICache and DCache in uboot, if disable them, then the network is work OK in kernel then can mount nfs filesystem later …
so, now the uboot and kernel both work OK for nfs boot.
[20090814]
1.after the uboot can do nfs boot the uImage, but find the uImage can not properly init the ethernet,can not read out the RevID of ethernet card, seems the SPI CS is not correct, is become low at a certain time, which one to set or influence the CS pin of ethernet. to be done to find out the reason.
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