tmp m25p40

!!! seems that the nand and SSP1(Nor chip m25p40) can not concurrently work,

for if use nand, will use naf alternative mode, it can not use SSP1, only use SSP2, so should to make sure we can use SSP2 to connect to Nor chip or not.

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//#include <asm/mach/flash.h>
#include <linux/spi/flash.h>

should add #include <asm/mach/gpio_registers.h>

and replace the old XXX_BASE+0x420 to AFSEL.

#define NOR_UBOOT_SIZE             (SZ_64K * 7) /* 0 – 0x70000 */
#define NOR_UBOOT_ENV_SIZE     (SZ_64K * 1) /* 0x70000 – 0x80000 */

static struct mtd_partition as353x_default_ssp_nor_part[] = {
[0] = {
.name = "Nor-Uboot",
.offset = 0,
.size   = NOR_UBOOT_SIZE,
},
[1] = {
.name = "Nor-Uboot-Env",
.offset = NOR_UBOOT_SIZE,
.size   = NOR_UBOOT_ENV_SIZE
},
}

static struct flash_platform_data spi_nor_flash = {
.type = "m25p40"; /* also can not set here, let driver auto probe it */
.name = "ssp-nor";
.parts = as353x_default_ssp_nor_part;
.nr_parts = ARRAY_SIZE(as353x_default_ssp_nor_part);
};

static const struct spi_board_info const as353x_spi_devices[] = {
#if 1
{            /* SSP NOR Flash chip */
.modalias = "m25p80", /* let driver: drivers/mtd/devices/m25p80.c can find this device */
.chip_select = 0,
.controller_data = (void *)GPIO_A4,
.max_speed_hz = 20 * 1000 * 1000,
.bus_num = 1, /* this device belong to SSP1 */
.platform_data = &spi_nor_flash,
/* .mode = , seems the as353x spi driver not process this mode setting, so not set here */
/* .irq = , m25p80 driver seems not use this irq, so not need set it */
},
#endif
{            /* SSP Eth enc28j60 controller */
.modalias = "enc28j60",
.chip_select = 1,
.controller_data = (void *)GPIO_G6,
.max_speed_hz = 15* 1000 * 1000,
.bus_num = 1,
.mode = SPI_CPOL,
.irq = IRQ_GPIOL2,
},
};

…
#ifdef CONFIG_AS353X_SPI1
ccuClearAlternativeModeBit(CCU_PWM); /* if not do this, is it means the GPIOA set to hw control, and default is alternative mode 1==SSP1 ? */
//ccuSetAlternativeModeBit(CCU_SSP1); /* should call this, but SSP_1 reg not alternative bit, why ??? */
SetRegBits32(CCUP_REG_XPA, CCUV__DS);
//ModRegBits32(IO_ADDRESS(AS353X_GPIOA_BASE) + 0x420, 0xe0, 0xe0);
ClrRegBits32(GPIOA_AFSEL, BIT(4)); /* bit4:CS, slave select for Motorola SPI  and Microwave */
ModRegBits32(GPIOA_AFSEL, 0xe0, 0xe0);/* bit5:SCLK, bit6:SDO, bit7: SDI */
#endif
…

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