/*
 * Set the initial DMA register values i.e. those for the first LLI
 * The next lli pointer and the configuration interrupt bit have
 * been set when the LLIs were constructed
 */
void pl08x_set_cregs(struct pl08x_txd *entry, int pl08x_chan_num)
{
	unsigned int reg;
	unsigned int chan_base = (unsigned int)pd.base
					+ PL08X_OS_CHAN_BASE;
	chan_base += pl08x_chan_num * PL08X_OS_CHAN;

	/* Wait for channel inactive */
	reg = readl(chan_base + PL08X_OS_CCFG);
	while (reg & PL08X_MASK_ACTIVE)
		reg = readl(chan_base + PL08X_OS_CCFG);

	writel(entry->csrc, chan_base + PL08X_OS_CSRC);
	writel(entry->cdst, chan_base + PL08X_OS_CDST);
	writel(entry->clli, chan_base + PL08X_OS_CLLI);
	writel(entry->cctl, chan_base + PL08X_OS_CCTL);
	writel(entry->ccfg, chan_base + PL08X_OS_CCFG);
	mb();
}